Verilog Parameter Usage
The following information about the verilog parameters is exteremly rare. I had struggled to find this information, at last some hit and trials made the way through.
The problem description:
Suppose you have a verilog code, for example a code for a simple register, which is parameterised. The width of the register is taken as parameter named ‘width’. You want to initialize any ‘wire’ type or ‘reg’ type with a value which has all ‘1′. How you will do it? Consider the following:
parameter width = 4;
reg [width-1:0] my_register;
always @(posedge clock or negedge reset)
if(reset) reg = 4′b1111;
else if……..
here we have used ‘4′ but what about if we would like to use, instead of ‘4′, a function of ‘width’?
Here is how you will do it:
always @(posedge clock or negedge reset)
if(reset) reg = {(width){1′b1}}
else if……………..
hey thanks! it took me a while to Google this!
np
’tis good to share knowledge with others!
Hello jack
Can i use use the parameter inside a for statement like
parameter x = 3;
for (i = 0; i< x; i++)
Jackey,
What you did is a concatenation of bits.
Maybe you would like to search about concatenation in Verilog.
Thanks for the help
Have you tried -1 as a solution?
It does not require WIDTH.
Have not had any problems using that.
No warnings or INFO messages – (yet).
Andy
Here all the 4 bits are 1. what if want something like following
if(reset) reg = 4′b1001;
and I want to parameterize the 4 with WIDTH
Sunjiv raises a good point here.
Sunjiv,
Here is your solution:
Use concatenation.
if(reset) reg = {{WIDTH-1{1′b0}},1′b1}};
for WIDTH = 4, this is equivalent to
if(reset) reg = {1′b0,1′b0,1′b0,1′b1};
is equivalent to
if(reset) reg = 4′b0001;
Ta-da!
Thanks to your website to clarrify my doubt on parameter